Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates, trapping layers or other physical phenomena, determine the data state of each cell.
The memory cells of a memory device are typically arranged in a memory array having a plurality of groups (e.g., blocks) that can be organized as series strings of memory cells. Support circuitry can be used to select an individual string of a number of strings of memory cells in a group of strings of memory cells in order to program, read, or erase a cell(s) of the selected string.
FIG. 1 illustrates typical prior art support circuitry 150, 151 for selecting and deselecting individual series strings of memory cells in respective selected and deselected memory blocks 100, 101. Since a number of memory blocks can share the same access lines (e.g., word lines) and data lines (e.g., bit lines), only the memory block that is being accessed for a particular memory operation (e.g., program, read, erase) should be selected.
FIG. 1 shows a memory block 100 that is selected for a particular memory operation (e.g., program, read, erase) and a memory block 101 that is deselected such that its memory cells are not affected by signals on the word lines WL0-WL32, bit line 110, and/or source 111. Each memory block 100, 101 is shown with two typical series strings 120-123 of memory cells that represent, for example, a plurality of series strings in each block (e.g., 0-15). Each series string 120-123 can be coupled to a respective drain select device 125-128 that can be used to selectively couple the respective series string to a bit line 110 responsive to a local drain select gate control signal SGD0-SGD15 and a respective source select device 130-133 that can be used to selectively couple the respective series string to the source 111 responsive to a local source select gate control signal SGS.
For purposes of clarity, the support circuitry 150, 151 shown represents the typical circuitry used for selectively coupling a single global word line GWL0 to a local word line WL0 and a single global drain select gate GSGD0 to a local drain select gate SGD0. For the selected block 100, a word line selecting transistor 103 and a drain select gate selecting transistor 105 are shown enabled by a high signal BLKSEL(n). A drain select gate deselecting transistor 106 is shown disabled by a low signal BLKSELb(n). Similarly, for the deselected block 101, a word line selecting transistor 107 and a drain select gate selecting transistor 108 are shown disabled by a low signal BLKSEL(n) while a drain select gate deselecting transistor 109 is shown enabled by a high signal BLKSELb(n).
It can be seen from FIG. 1 that each word line can be selected by one selecting/deselecting transistor 103, 107 and each drain select gate can be selected by two selecting/deselecting transistors 105, 108 and 106, 109 respectively. While it is not shown, the source select gates can also each use two selecting/deselecting transistors. Since a typical memory device might have hundreds of thousands of word lines and select gates, it can be appreciated that the support circuitry for the memory device can use a considerable amount of integrated circuit die real estate that might better be used by additional memory cells for greater memory density.